The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for forming a contact in a semiconductor device with increased contact area and reduced leakage current.
As patterns in highly integrated memory devices below 0.100 μm become micronized, contact hole spacing has decreased. Accordingly, a high aspect ratio has caused margins to rapidly decrease, and thus, spacing distance between lines also have decreased. The source/drain contact resistance (Rc) increases substantially when the hole spacing and the spacing distance between lines decreases.
FIGS. 1A and 1B illustrate cross-sectional views showing a typical method for forming a contact in a semiconductor device.
Referring to FIG. 1A, a plurality of gate patterns are formed over a substrate 11. Each gate pattern includes a gate insulation layer 12, a gate electrode 13, and a gate hard mask layer 14. Cell spacers 15 are formed over the gate patterns. In more detail, a cell spacer layer is formed over the substrate 11 and the gate patterns. The cell spacer layer may include a nitride-based layer. An insulation layer is formed over the cell spacer layer to sufficiently gap-fill between the gate patterns. An etching process for forming a landing plug contact is performed. That is, the insulation layer is etched until the etching stops at the cell spacer layer to form trenches. This creates patterned insulation layers 16.
A buffer oxide layer is formed over the resultant substrate structure. The buffer oxide layer is formed with poor step coverage. That is, the buffer oxide layer is formed to have a small thickness over upper surfaces of the substrate 11 and sidewalls of the gate patterns and have a large thickness over an upper portion of the gate patterns, having an overhang structure. An etch-back process is performed on the buffer oxide layer to form contact holes 17 exposing the upper surfaces of the substrate 11 between the gate patterns. This creates patterned buffer oxide layers 18. During the etch-back process, portions of the cell spacer layer over the upper surfaces of the substrate 11 are also etched away. This creates the cell spacers 15. Since the etch-back process of the buffer oxide layer includes a dry etching process using plasma, the substrate damage 19 is often generated by plasma ions during the etch-back process.
Referring to FIG. 1B, a post treatment is performed to remove the substrate damage 19. The post treatment includes performing an etching process referred to as a light etch treatment (LET). Such post treatment often generates a substrate depression 20.
The typical method increases the depth of the substrate depression 20 by the LET process which reduces contact resistance of the source/drain contacts, by increasing the contact area. However, the increased depth may cause leakage current, and refresh may be deteriorated. Also, although a certain depth in the substrate depression 20 is generally needed to control the cell threshold voltage (Vth) and the refresh, this is typically not enough to increase the contact resistance value. Thus, a method for forming a contact that can maintain a certain depth of the substrate depression and improve contact resistance may be necessary.